Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Clock divider

Hi all Again with VHDL problems :p I need a clock divider to run a Z80. My board fréquency is 50Mhz and I need 3,57Mhz. I found this code but it doesn't seem working with all "constant CLK_S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes, that's a straightforward way to generate a divided clock with 50% duty cycle. As long as you don't transfer data from the 50 MHz clock domain to the 3.57 MHz domain, it won't involve any timing issues. Many Altera devices have the option to generate low output frequencies like 3.57 MHz in the PLL, by the way.