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I found this code but it doesn't seem working with all "constant CLK_SLOW_FREQ"
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What do you mean? The code does work as a 14:1 clock divider, output is one input period high, as expectable. It could e.g. work as a clock enable in a 50 MHz clock domain.
The second code generates a similar output signal, but with 12:1 ratio, output frequency is 4.167 MHz. The coding style is unnecessarily complicated, I think. Due to the combinational generation of clk_en, the output has glitches. Either if the output is intended as clock or clock enable, I would register it. In case of the divided clock, you avoid glitches, for the clock divider, you improve setup time.
But what do you want to achieve exactly?
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