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ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

clock constraint

Hi,

My design includes two PLLs that generate clocks with the same frequency (128MHz) but with different phases. Both clocks feed into the "clkctrl IP," which selects the output clock through software (two input clocks, one output clock, and a select bit).

My question is how should I define these clocks? The ones generated by the PLLs are defined as "clock generated clocks," but what about the output clock from the "clkctrl IP"? Should I define it as a "clock generated clock" or use "create clock"?

Additionally, I have two source clocks for the output clock. How should I handle the definition of the source clock in this constraint?

Timing

4 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Depending on your target device, for the clocks output from the PLLs, all you really need is to add derive_pll_clocks to your .sdc file.

    The clock control block is basically a clock mux in this case, so you need to create additional generated clocks as "points of reference" both targeted to the output of the clock control block and then use set_clock_groups to indicate that only one clock is active at a time. Here's an example from a training class I took. You don't need the two initial create_clock commands since those are the clocks coming from the PLL and are created with derive_pll_clocks. The example shows what it would be if the clocks were coming directly from clock input pins instead of from a PLL.

     

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    I believe your inquiries are answered.

    With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

    Thank you and have a great day!


    Best Regards,

    Richard Tan