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ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

clock constraint

Hi, My design includes two PLLs that generate clocks with the same frequency (128MHz) but with different phases. Both clocks feed into the "clkctrl IP," which selects the output clock through softwa...
Timing
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

I believe your inquiries are answered.

With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!


Best Regards,

Richard Tan