clock constraint

Depending on your target device, for the clocks output from the PLLs, all you really need is to add derive_pll_clocks to your .sdc file.

The clock control block is basically a clock mux in this case, so you need to create additional generated clocks as "points of reference" both targeted to the output of the clock control block and then use set_clock_groups to indicate that only one clock is active at a time. Here's an example from a training class I took. You don't need the two initial create_clock commands since those are the clocks coming from the PLL and are created with derive_pll_clocks. The example shows what it would be if the clocks were coming directly from clock input pins instead of from a PLL.