CLK-30028 - Invalid Generated Clock

hi

I repeat my original Q,

I have violation notification "CLK-30028: Invalid Generated Clock" . the reason as I understand :No paths exist between the clock target and its clock source

but this is a clock coming out of the PLL and it seems all is define correctly .

the critical warning

Status: FAIL
Severity: High
Number of violations: 1
Rule Parameters: max_violations = 5000
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; CLK-30028 - Invalid Generated Clock ;
+---------+------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------+
; Clock ; Target ; Reason ; Waived ;
+---------+------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------+
; pll_clk ; step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0] ; No paths exist between the clock target and its clock source. Assuming zero source clock latency. ; ;
+---------+------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------+

the output of the report_clocks

; pll_clk ; Generated ; 50.000 ; 20.0 MHz ; 0.000 ; 25.000 ; ; 5 ; 1 ; ; ; ; ; false ; gclk_3_in ; step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|refclk[0] ; { step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0] } ;

the clock definition :

create_generated_clock -name {pll_clk} -source [get_pins {step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|refclk[0]}] [get_pins {step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]}] -multiply_by {1} -divide_by {5}

Hi there, I have checked and the Timing Analyzer shows that all PLL clocks are automatically generated by the SDC files generated alongside the PLL IP. No user action is required.

So why you want to apply the generated clock contraints? BTW as constraint applied by 'derive_pll_clocks' will follow your setting in IP setting your custom contraint will overwrite this. I think this warning may related to the 3rd party tools, which cause the overwiting failed.

I think you may try to apply the contraint you want refering to the following link.

https://www.intel.com/content/www/us/en/docs/programmable/683122/23-4/clock-frequencies.html

1. "So why you want to apply the generated clock constraints?" , I don't want to generated clock constantans , I just want to understand the warning which is pasted 2 times in this post .

2. "derive_pll_clocks" how come , this constraint is working on Stx10 ? see previous responses about "derive_pll_clocks"

Hi there, for the reason I ask why you want to apply the constraint is that we are not sure if it's suitable to apply this to the pll clock. We can't figure out what the software will do, as it isn't a recommended practice and may cause some strange warning which won't show the root cause.

Like here, I can also see the path between the nodes in the constraint, so it might be a warning which doesn't show the true reason.

Hi ,

so what is the bottom line , what can I provide in order to understand the root cause of the warning ?

Hi there, I think the pll wasn't generated completely. When directly using Quartus for synthesis, all the constraints for pll will be generated automatically. As you are using 3rd party synthesis tool, some constraint may be missing. The path exists, this warning just shows the software assumes there are no latency between these two nodes.

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