CLK-30028 - Invalid Generated Clock

Hi there, I have checked and the Timing Analyzer shows that all PLL clocks are automatically generated by the SDC files generated alongside the PLL IP. No user action is required.

So why you want to apply the generated clock contraints? BTW as constraint applied by 'derive_pll_clocks' will follow your setting in IP setting your custom contraint will overwrite this. I think this warning may related to the 3rd party tools, which cause the overwiting failed.

I think you may try to apply the contraint you want refering to the following link.

https://www.intel.com/content/www/us/en/docs/programmable/683122/23-4/clock-frequencies.html