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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

CLK-30028 - Invalid Generated Clock

Hi I'm trying to define generated clock out of the pll. and I get the following violation notification "CLK-30028: Invalid Generated Clock" https://www.intel.la/content/www/xl/es/programmable/quar...
Timing
TingJiangT_Intel's avatar
TingJiangT_Intel
Icon for Contributor rankContributor
1 year ago

Hi there, I think the pll wasn't generated completely. When directly using Quartus for synthesis, all the constraints for pll will be generated automatically. As you are using 3rd party synthesis tool, some constraint may be missing. The path exists, this warning just shows the software assumes there are no latency between these two nodes.