CLK-30028 - Invalid Generated Clock

Hi there, for the reason I ask why you want to apply the constraint is that we are not sure if it's suitable to apply this to the pll clock. We can't figure out what the software will do, as it isn't a recommended practice and may cause some strange warning which won't show the root cause.

Like here, I can also see the path between the nodes in the constraint, so it might be a warning which doesn't show the true reason.