CLK-30028 - Invalid Generated Clock

hi

I repeat my original Q,

I have violation notification "CLK-30028: Invalid Generated Clock" . the reason as I understand :No paths exist between the clock target and its clock source

but this is a clock coming out of the PLL and it seems all is define correctly .

the critical warning

Status: FAIL
Severity: High
Number of violations: 1
Rule Parameters: max_violations = 5000
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; CLK-30028 - Invalid Generated Clock ;
+---------+------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------+
; Clock ; Target ; Reason ; Waived ;
+---------+------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------+
; pll_clk ; step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0] ; No paths exist between the clock target and its clock source. Assuming zero source clock latency. ; ;
+---------+------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+--------+

the output of the report_clocks

; pll_clk ; Generated ; 50.000 ; 20.0 MHz ; 0.000 ; 25.000 ; ; 5 ; 1 ; ; ; ; ; false ; gclk_3_in ; step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|refclk[0] ; { step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0] } ;

the clock definition :

create_generated_clock -name {pll_clk} -source [get_pins {step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|refclk[0]}] [get_pins {step_ana_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]}] -multiply_by {1} -divide_by {5}