Forum Discussion
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to propagate through chain and in moment when STOP occurs, propagation is sampled by registers. To do so, all it takes is to set all the bits of the first operand (input a) to ‘1’ and the bits of the second operand to ‘0’ (input b). Code which works fine for me is :
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DelayLine is generic ( DATA_WIDTH : natural := 20 ); port ( output: out signed ((DATA_WIDTH-1) downto 0); a: in signed ((DATA_WIDTH-1) downto 0); b: in signed ((DATA_WIDTH-1) downto 0); START: in std_logic ); end DelayLine; architecture rtl of DelayLine is SIGNAL reg: signed ((DATA_WIDTH-1) downto 0); SIGNAL buf: signed ((DATA_WIDTH-1) downto 0); SIGNAL STOP: std_logic; SIGNAL I: integer := 0; begin process (START) variable s : signed ((DATA_WIDTH) downto 0); begin s := ('0' & a) + ('0' & b) + ('0' & START); buf<=s((DATA_WIDTH-1) downto 0); if (falling_edge(START)) then output<=buf((DATA_WIDTH-1) downto 0); end if; end process; end rtl; PROBLEM: Currently my only idea how to supply every adder block with two required signals ('1' and '0') is to make another two registers; one register with ones and other with zeros. Such solution is making a lots of problems in my design. My question is it possible to make some more simple circuit which will supply adders with ones and zeros. I have tried with nonsequential registers (All elements forced to high or low state) but then my carry chain gets deformation.37 Replies
Altera_ForumUsing any internal logic as delay elements is doomed to failure - everything in the chip is affected by PVT (process, voltage, temperature) ie. the given delay will vary depending on these three factors and is not deterministic.
Why are you trying to do this? You will be unable to simulate this code in RTL simulation, has it has no delays in it. (and the fact you have not included all the signals in the sensitivity list, meaning you will get missmatches between hardware and simulation if it even works). What is the goal of your design?- Altera_Forum
I am trying to implement time to digital converter. I have read some scientific articles about this topic, bellow is link to one interesting article. I am FPGA beginner so scientific articles like this give me hope that it is possible to do :).
Design of 42 ps TDC on low cost FPGA https://webcache.googleusercontent.com/search?q=cache:xmqa13wf6n8j:https://www.thinkmind.org/download.php%3farticleid%3dsensorcomm_2015_2_20_10046+&cd=1&hl=hr&ct=clnk&gl=hr. - Altera_Forum
Possibly interesting - but this is an advanced topic for people with good knowledge of FPGAs. The tools they describe using are the floorplanner, manually placing the gates and registers to get something close to the timing they desire. It explicitly states that using HDL to try and acheive the goal you describe doesnt work. (in the link you posted, none of the figures are loading)
I highly suggest you leave this topic for now, and learn about HDLs and FPGAs. Learn the tools and how to use them. Trying to do what you are trying without understanding FPGAs is just not going to get you anywhere. - Altera_Forum
It also does not even touch on the PVT issue - ie. two chips will never get the same results.
- Altera_Forum
How do use TDC for?
- Altera_Forum
Sorry I didn't understand quite well what you are asking me. I have project in which I need to implement two TDC methods in FPGA. For now I have made counter based TDC (4 phased clocks with resolution if 1.25 ns). Delay line is next step but I have many problems. Currently the biggest problem is deformation of delay line when I try to connect two inputs of every adder to GND and VCC. When I do this with sequential logic (shift registers) , delay line is formed well.
- Altera_Forum
I remember Dr. Wu Jinyuan introduced how to implement TDC inside FPGA. Sometime you need assign allocation manually. According Dr. Wu's method, i have implemented TDC inside FPGA sucessfully.
http://www.alteraforum.com/forum/attachment.php?attachmentid=12072&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12073&stc=1 - Altera_Forum
Currently I am having problems with manual placement of resources. I know how to create delay line. Problem starts with manual placement of resources; for example when I try to place START block at the beginning of the delay line, line gets deformation (random placement of elements for example or slight deformations). I really don't understand why manual placement of element affects delay line. Here is example of delay line without deformation:
https://www.alteraforum.com/forum/attachment.php?attachmentid=12114 https://www.alteraforum.com/forum/attachment.php?attachmentid=12114 Here is example of deformed delay line: https://www.alteraforum.com/forum/attachment.php?attachmentid=12115 - Altera_Forum
Hi Jurke,
I am too interested in this topic and by now collected tonnes of scientific papers (from ieee) on this subject, there is a number of quite successful designs however, achieving high linearity is the main issue on fpga based design. Jerry mentioned Dr. Wu Jinyuan work (Jerry, if you indeed implemented may be you may share more on this?). it is so called wave union which allow sampling TDC with a pulse pattern and then building up ram based lut which contains basically the correction to the TDC output code. I am thinking about different method, but this is for second stage, first stage is how to build the TDC itself. I investigated few approaches, and now considering two methods, vernier type based on two ring oscillator, very simple, easy to calibrate, good resolution and free from non-linearity. The main problem is the ring oscilator itself, although I did not invest much time on this, my first attempts fails so far, the oscillators do not start :-( Another way is to build in the way you do by using adder, simple to design, yet problems with non-linearity due of inter LAB bins. Manual placing is quite simple if you have chip planner working (license). I used two steps, first compiled as is, then in chip planner created logiclock region of the size design is calling for, then dragging manually the cells one by one in to the new region. Last assign the logic region to TDC entiry and compile. It is quite laborious work especially if you need couple of hundreds of cells. However, Quartus will place automatically the bins in ONE (important!) column if the design is based on carry adder, at list for me it is working, the only step I do is to allocate a region by logiclock. Currently I am busy with design based on low level primitives, I found some suitable code for Cycloneiii however for some reason it is not going to synthesis any thing for my Cii, although the LE is exactly the same. The reason for turning to low level is as you stated in the first post, how to allocate input signals to adders, so far I did not solve this problem in reasonable manner, curious if you succeed and how... - Altera_Forum
Hi parasole,
I am glad to see somebody with the same problem. Currently I am busy but I will contact you tomorrow, so we can discuss more about this topic !
