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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Possibly interesting - but this is an advanced topic for people with good knowledge of FPGAs. The tools they describe using are the floorplanner, manually placing the gates and registers to get something close to the timing they desire. It explicitly states that using HDL to try and acheive the goal you describe doesnt work. (in the link you posted, none of the figures are loading)

I highly suggest you leave this topic for now, and learn about HDLs and FPGAs. Learn the tools and how to use them. Trying to do what you are trying without understanding FPGAs is just not going to get you anywhere.