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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Sorry I didn't understand quite well what you are asking me. I have project in which I need to implement two TDC methods in FPGA. For now I have made counter based TDC (4 phased clocks with resolution if 1.25 ns). Delay line is next step but I have many problems. Currently the biggest problem is deformation of delay line when I try to connect two inputs of every adder to GND and VCC. When I do this with sequential logic (shift registers) , delay line is formed well.