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Honored Contributor
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_ForumHonored Contributor
Honored ContributorI remember Dr. Wu Jinyuan introduced how to implement TDC inside FPGA. Sometime you need assign allocation manually. According Dr. Wu's method, i have implemented TDC inside FPGA sucessfully.
http://www.alteraforum.com/forum/attachment.php?attachmentid=12072&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12073&stc=1
