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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I am trying to implement time to digital converter. I have read some scientific articles about this topic, bellow is link to one interesting article. I am FPGA beginner so scientific articles like this give me hope that it is possible to do :).

Design of 42 ps TDC on low cost FPGA

https://webcache.googleusercontent.com/search?q=cache:xmqa13wf6n8j:https://www.thinkmind.org/download.php%3farticleid%3dsensorcomm_2015_2_20_10046+&cd=1&hl=hr&ct=clnk&gl=hr.