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Honored Contributor
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_ForumHonored Contributor
Honored ContributorUsing any internal logic as delay elements is doomed to failure - everything in the chip is affected by PVT (process, voltage, temperature) ie. the given delay will vary depending on these three factors and is not deterministic.
Why are you trying to do this? You will be unable to simulate this code in RTL simulation, has it has no delays in it. (and the fact you have not included all the signals in the sensitivity list, meaning you will get missmatches between hardware and simulation if it even works). What is the goal of your design?
