Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

Hi Jurke,

I am too interested in this topic and by now collected tonnes of scientific papers (from ieee) on this subject, there is a number of quite successful designs however, achieving high linearity is the main issue on fpga based design.

Jerry mentioned Dr. Wu Jinyuan work (Jerry, if you indeed implemented may be you may share more on this?). it is so called wave union which allow sampling TDC with a pulse pattern and then building up ram based lut which contains basically the correction to the TDC output code. I am thinking about different method, but this is for second stage, first stage is how to build the TDC itself.

I investigated few approaches, and now considering two methods, vernier type based on two ring oscillator, very simple, easy to calibrate, good resolution and free from non-linearity. The main problem is the ring oscilator itself, although I did not invest much time on this, my first attempts fails so far, the oscillators do not start :-( Another way is to build in the way you do by using adder, simple to design, yet problems with non-linearity due of inter LAB bins. Manual placing is quite simple if you have chip planner working (license). I used two steps, first compiled as is, then in chip planner created logiclock region of the size design is calling for, then dragging manually the cells one by one in to the new region. Last assign the logic region to TDC entiry and compile. It is quite laborious work especially if you need couple of hundreds of cells. However, Quartus will place automatically the bins in ONE (important!) column if the design is based on carry adder, at list for me it is working, the only step I do is to allocate a region by logiclock. Currently I am busy with design based on low level primitives, I found some suitable code for Cycloneiii however for some reason it is not going to synthesis any thing for my Cii, although the LE is exactly the same. The reason for turning to low level is as you stated in the first post, how to allocate input signals to adders, so far I did not solve this problem in reasonable manner, curious if you succeed and how...