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Altera_Forum's avatar
Altera_Forum
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9 years ago

Can't place all Ram Cells in the design Issue

Hi,

In my design I'm facing a weird problem. I have a ADC IP core in my design and whenever I'm enabling the debug path for the ADC the analysis and the synthesis of the design passes the test successfully but the in the fitter it throws an error "Can't place all RAM cells in the design. Whenever I'm disabling the ADC debug path there is no such issue. Can anyone help me with this issue ?

Note : In the Signal Tap it shows Memory 187/182 whenever the error is thrown wheres in the event of successful compilation it shows Memory 148/182

I've also attached a screen shot of this.

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I'm sure the debug logic stores data from the ADC to be analyzed, which must be done in memory. You would have to remove memory from other parts of your design in order to free up some space. (You may want to run a test design that purely does the ADC debug and doesn't have the rest of your design in it...)

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    It's not a weird problem, it is expected behavior. The SIGNAL TAP logic analyzer function needs memory to store the captured data, and it uses BLOCK RAM. So when you enable SIGNAL TAP, it will use up some BLOCK RAM.

    So, as suggested above, either subset your design, and cut out other BLOCK RAM intensive portions temporarily, or possibly fine tune your SIGNAL TAP debug logic. Reduce the number of captured signals; reduce the depth of the capture. Both of these will reduce the BLOCK RAM requirements. Your usage with SIGNAL TAP is 187/182, and 148/182 without, so your SIGNAL TAP configuration is using 39 BLOCK RAMs for storage. Halve this number and you should be OK.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi ak6dn,

    From the Attached file you can seen that I'm not even capturing any signals in Signal Tap when I'm enabling the debug path for ADC core. Could you please suggest how to remove memory from other parts of my design ?

    Thanks,
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The attached thumbnails in the first post are basically illegible when viewed so they are not useful. SignalTap does appear to be enabled and it does use block ram.

    As to how to remove memory from other parts of your design, only you can answer that, really.

    Suggestions are make any RAM buffers that exist smaller (ie, less deep), or more realistically you may have to eliminate entire portions of logic temporarily.