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Altera_Forum
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9 years ago

Can't place all Ram Cells in the design Issue

Hi, In my design I'm facing a weird problem. I have a ADC IP core in my design and whenever I'm enabling the debug path for the ADC the analysis and the synthesis of the design passes the test ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi ak6dn,

From the Attached file you can seen that I'm not even capturing any signals in Signal Tap when I'm enabling the debug path for ADC core. Could you please suggest how to remove memory from other parts of my design ?

Thanks,