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Altera_Forum's avatar
Altera_Forum
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10 years ago

Can't place all Ram Cells in the design Issue

Hi, In my design I'm facing a weird problem. I have a ADC IP core in my design and whenever I'm enabling the debug path for the ADC the analysis and the synthesis of the design passes the test ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I'm sure the debug logic stores data from the ADC to be analyzed, which must be done in memory. You would have to remove memory from other parts of your design in order to free up some space. (You may want to run a test design that purely does the ADC debug and doesn't have the rest of your design in it...)