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Altera_Forum
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9 years ago

Can't place all Ram Cells in the design Issue

Hi, In my design I'm facing a weird problem. I have a ADC IP core in my design and whenever I'm enabling the debug path for the ADC the analysis and the synthesis of the design passes the test ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It's not a weird problem, it is expected behavior. The SIGNAL TAP logic analyzer function needs memory to store the captured data, and it uses BLOCK RAM. So when you enable SIGNAL TAP, it will use up some BLOCK RAM.

So, as suggested above, either subset your design, and cut out other BLOCK RAM intensive portions temporarily, or possibly fine tune your SIGNAL TAP debug logic. Reduce the number of captured signals; reduce the depth of the capture. Both of these will reduce the BLOCK RAM requirements. Your usage with SIGNAL TAP is 187/182, and 148/182 without, so your SIGNAL TAP configuration is using 39 BLOCK RAMs for storage. Halve this number and you should be OK.