Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Can't place all Ram Cells in the design Issue

Hi, In my design I'm facing a weird problem. I have a ADC IP core in my design and whenever I'm enabling the debug path for the ADC the analysis and the synthesis of the design passes the test ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The attached thumbnails in the first post are basically illegible when viewed so they are not useful. SignalTap does appear to be enabled and it does use block ram.

As to how to remove memory from other parts of your design, only you can answer that, really.

Suggestions are make any RAM buffers that exist smaller (ie, less deep), or more realistically you may have to eliminate entire portions of logic temporarily.