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New ContributorCan Quartus Prime Platform Designer Verification IP only be used for Intel/Altera designs?
The Intel Quartus Prime Platform Designer contains several verification IP for for AXI bus and also clock and reset BFM. Here is the image:
The AXI is also used in Xilinx designs and Microsemi designs among other places. It is a popular on-chip interface standard.
Are these IP available in the free web version of the design?
More importantly, can these IP be used when developing a design that is not targeted to Intel device or the licence prevents that?
4 Replies
ShengN_alteraSuper Contributor
Hi,
Are these IP available in the free web version of the design?
Yes, these IPs are available in the Quartus Lite Version.
More importantly, can these IP be used when developing a design that is not targeted to Intel device or the licence prevents that?
These bfm IPs can be used with third party ip or design on simulation functionality check. But, the third-party ip or design need to be included in Quartus and simulated using Quartus simulator tool. Because these bfm IPs are dependent on Quartus simulator tool (libraries, license, .etc)
Thanks,
Regards,
Sheng
okhajutWhat do you mean by "Quartus simulator tool"? Simulation is done using QuestaSim, ActiveHDL e.t.c. To run simulation we need to compile some source files and then elaborate the design and run the testbench.
I do not understand your reply for this reason.
- ShengN_altera
Hi,
Yes Questasim, Active-HDL etc, I mean the supported simulator and vendor check this link for the list https://www.intel.com/content/www/us/en/docs/programmable/683870/24-1/supported-simulators.html
- ShengN_altera
Hi,
May I know do you have any further update or concern on previous post?
Thanks,
Regards,
Sheng
