Forum Discussion
okhajut
New Contributor
New ContributorCan Quartus Prime Platform Designer Verification IP only be used for Intel/Altera designs?
The Intel Quartus Prime Platform Designer contains several verification IP for for AXI bus and also clock and reset BFM. Here is the image: The AXI is also used in Xilinx designs and Micro...
okhajutNew Contributor
New ContributorWhat do you mean by "Quartus simulator tool"? Simulation is done using QuestaSim, ActiveHDL e.t.c. To run simulation we need to compile some source files and then elaborate the design and run the testbench.
I do not understand your reply for this reason.
