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Altera_Forum
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Honored ContributorCan actual delays be implemented with .sdc constrains?
Hi,
Can actual delays be implemented with .sdc constrains? I will try to explain what i want to achieve: Lets say i have PLL with two output clocks "pll_c0" and "pll_c1". "pll_c0" drives DDR output register which is connected to output pin "clkout" "pll_c1" drives DDR output register which is connected to dataout[4..0] pins. By changing "pll_c1" clock phase i can change Tco ("clkout" to whole dataout[4..0]). But is there something i can do to add even more delay to lets say single pin dataout[4]? I have tried to apply set_output_delay to each individual pins with different Tsu and Th times but while testing on hardware i dont see any difference. My .sdc looks like:# Base clocks
create_clock -period 5 -name clk
# PLL
create_generated_clock -name pll_c0
-source ]
-phase 0 ]
create_generated_clock -name pll_c1
-source ]
-phase 0 ]
# Output clk pin
create_generated_clock -name clkout
-source .altgpio_bit_i|out_path_ddr.fr_out_data_ddio|dataout}]
# Output constraints
set_output_delay -max $Tsu
-clock }]
set_output_delay -min -$Th
-clock }]
set_output_delay -max $Tsu
-clock
-clock_fall }] -add_delay
set_output_delay -min -$Th
-clock
-clock_fall }] -add_delay
14 Replies
Altera_ForumBut it should try get more Tsu time in dataout[0] and more Th time in dataout[1]?
Is my understanding correct that with these constrains I am saying that i want dataout[0] valid 1ns before clkout and 0.5 ns after?
And with these lines i want dataout[1] valid 0.5ns before clkout and 1 ns after?# For bus bit 0 set_output_delay -max 1.0 -clock }] set_output_delay -min -0.5 -clock }] set_output_delay -max 1.0 -clock -clock_fall }] -add_delay set_output_delay -min -0.5 -clock -clock_fall }] -add_delay
If my constrains correct then in dataout[0] case fitter should try to make less delay to achieve positive slac on Tsu requirement and Th requirement should require less effort? For dataout[1] fitter should try to add more delay to achieve Th requirement and Tsu requirement should require less effort?# For bus bit 1 set_output_delay -max 0.5 -clock }] set_output_delay -min -1.0 -clock }] set_output_delay -max 0.5 -clock -clock_fall }] -add_delay set_output_delay -min -1.0 -clock -clock_fall }] -add_delay- Altera_Forum
your interpretation of valid window is correct in both cases
The tool does not care about comparing these values. It just wants to pass timing and it sees wide transition window available In short sdc is not meant for fine tuning of delays. I don't see why you need that - Altera_Forum--- Quote Start --- I don't see why you need that --- Quote End --- + There is some hardware issues in system i use. FPGA is connected to external device - IC. We have equally matched short PCB traces connecting FPGA and external IC. Due to some issues in external device some bus bits has to be delayed more then others in order to capture them correctly in external device. So as a workaround I want to implement separate delays for each bus bit in FPGA. And I need a suggestion on how to do that.
- Altera_Forum--- Quote Start --- + There is some hardware issues in system i use. FPGA is connected to external device - IC. We have equally matched short PCB traces connecting FPGA and external IC. Due to some issues in external device some bus bits has to be delayed more then others in order to capture them correctly in external device. So as a workaround I want to implement separate delays for each bus bit in FPGA. And I need a suggestion on how to do that. --- Quote End --- For that purpose I will set the set_output_delay constraints per each bit based on its required valid window and leave that to the timing tool to see if it passes io timing. If it doesn't pass timing then you might look at other command options such as set_net_delay (though I don't use it). I assume your IF is source synchronous and that you are using fast output registers.
