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Altera_Forum
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9 years ago

Can actual delays be implemented with .sdc constrains?

Hi, Can actual delays be implemented with .sdc constrains? I will try to explain what i want to achieve: Lets say i have PLL with two output clocks "pll_c0" and "pll_c1". "pll_c0" d...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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I don't see why you need that

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+

There is some hardware issues in system i use. FPGA is connected to external device - IC. We have equally matched short PCB traces connecting FPGA and external IC. Due to some issues in external device some bus bits has to be delayed more then others in order to capture them correctly in external device. So as a workaround I want to implement separate delays for each bus bit in FPGA. And I need a suggestion on how to do that.