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There is some hardware issues in system i use. FPGA is connected to external device - IC. We have equally matched short PCB traces connecting FPGA and external IC. Due to some issues in external device some bus bits has to be delayed more then others in order to capture them correctly in external device. So as a workaround I want to implement separate delays for each bus bit in FPGA. And I need a suggestion on how to do that.
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For that purpose I will set the set_output_delay constraints per each bit based on its required valid window and leave that to the timing tool to see if it passes io timing. If it doesn't pass timing then you might look at other command options such as set_net_delay (though I don't use it). I assume your IF is source synchronous and that you are using fast output registers.
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