Can actual delays be implemented with .sdc constrains?

But it should try get more Tsu time in dataout[0] and more Th time in dataout[1]?

Is my understanding correct that with these constrains I am saying that i want dataout[0] valid 1ns before clkout and 0.5 ns after?

# For bus bit 0 
set_output_delay    -max 1.0 
                        -clock  }]
                        
set_output_delay    -min -0.5 
                        -clock  }]                        
                        
set_output_delay    -max 1.0 
                        -clock  
                        -clock_fall }] -add_delay
                                            
set_output_delay    -min -0.5 
                        -clock  
                        -clock_fall }] -add_delay

And with these lines i want dataout[1] valid 0.5ns before clkout and 1 ns after?

# For bus bit 1
set_output_delay    -max 0.5 
                        -clock  }]
                        
set_output_delay    -min -1.0 
                        -clock  }]                        
                        
set_output_delay    -max 0.5 
                        -clock  
                        -clock_fall }] -add_delay
                                            
set_output_delay    -min -1.0 
                        -clock  
                        -clock_fall }] -add_delay

If my constrains correct then in dataout[0] case fitter should try to make less delay to achieve positive slac on Tsu requirement and Th requirement should require less effort?

For dataout[1] fitter should try to add more delay to achieve Th requirement and Tsu requirement should require less effort?