In both the screenshot attached, I can see only one clock, which is wClk. Are you using a SCFIFO or DCFIFO? Which mode ( Legacy mode / Show-ahead mode) you are using for both the FIFO?
I did some further tests and I can bring some light into that issue. I analyzed it further and used the "Events mode" display in Modelsim.
I have now two examples where the same input is send to the FIFO. One time it behaves properly one time it fails.
The following situation is fine:
No signal or just the request signals are delayed with 23ps -> simulation works as you would expect.
In "Event Display mode" one can see that the clock is the first event and the read request signal comes later in the events.
The following situation it fails:
All the signals (including clock) are delayed by the same amount of time (23ps). So all the signals arrive the FIFO at the same time (as in the working situation described above)
In "Event Display mode" one can see that for any reason the read request signal is computed first. -> So with the next clock cycle (which actually had the rising edge at the same time as the request signal) the output is changed -> reason for the to early output.
So the behavior of that FIFO simulation model is weird. In my opinion if I look at it as a black box it should behave the same way if I input the same signals at any time!
Of course it is not the usual case to delay the clock signal and it is an edge case.
I created two test cases. The behavior for both test cases are the same. The output signal is high at positive edge of the rdclk when rdreq is high. Attached are the waveforms for same rdclk & wrclk and different rdclk & wrclk.
Have you read my previous reply? It seems that in my case Modelsim changed the priority of the input signals and the read request signal was computed before the clock signal! As I wrote above one can see it with event mode enabled.
I have no idea why that happened, I will not further investigate on it.
The last screenshot captures only the beginning of the waveform and there is no change of the clock signal and output data. Could you provide a full waveform with a few clock signals and changes of the output data?
Hi Erich, from your forum post, not only forum got worst, also support people seems don't read messages before reply.
Are you Altera centric or use other competitor?
I collected some critics to new Altera behavior, I am just searching for information about bug on simulation release, hardware and correlated.
Most of time simulator crash or report error on VHDL syntax, valid syntax. I simulate on thirdy party or competitor to check just IP core.
When I come back to Quartus design sometimes work and no idea of how to close timing and synthesis to get things work.
I feel this forum is not the best, are you on a neutral one like http://www.fpgadeveloper.com/? Can we join there to get a free of fear opinion about not least share opinion about what to do in the future?
I never used Altera from MM Pal age, Philips PLA (nicr fuse) and Xilinx XACT to mention few.
I migrated to Altera near 2005, designed on near all firm. Luckily speaking I never made large number on this firm.
Previous week I told my custom I fear I am not able to complete design and upset with me due I choosed Altera, made prototypes and fail at production test stage. :(
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