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EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

BUG in simulation library for dcfifo_mixed_widths with Modelsim

If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi YY!

Thank you for your reply!

Have you read my previous reply? It seems that in my case Modelsim changed the priority of the input signals and the read request signal was computed before the clock signal! As I wrote above one can see it with event mode enabled.

I have no idea why that happened, I will not further investigate on it.

How to continue?

Best regards,

Erich