BUG in simulation library for dcfifo_mixed_widths with Modelsim

Hi YY!

Please read my first post carefully.

Here are the parameters:

dcfifo_mixed_widths dcfifo_mixed_widths_component (

.rdclk (rdclk),

.wrclk (wrclk),

.wrreq (wrreq),

.aclr (aclr),

.data (data),

.rdreq (rdreq),

.wrempty (sub_wire0),

.wrfull (sub_wire1),

.q (sub_wire2),

.rdempty (sub_wire3),

.rdfull (sub_wire4),

.wrusedw (sub_wire5),

.rdusedw (sub_wire6));

defparam

dcfifo_mixed_widths_component.add_usedw_msb_bit = "ON",

dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",

dcfifo_mixed_widths_component.lpm_numwords = P_BUFFER_SIZE,

dcfifo_mixed_widths_component.lpm_showahead = "ON",

dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",

dcfifo_mixed_widths_component.lpm_width = P_INPUT_WIDTH,

dcfifo_mixed_widths_component.lpm_widthu = P_INPUT_FILL_WIDTH,

dcfifo_mixed_widths_component.lpm_widthu_r = P_OUT_FILL_WIDTH,

dcfifo_mixed_widths_component.lpm_width_r = P_OUTPUT_WIDTH,

dcfifo_mixed_widths_component.overflow_checking = "ON",

dcfifo_mixed_widths_component.rdsync_delaypipe = 4,

dcfifo_mixed_widths_component.read_aclr_synch = "ON",

dcfifo_mixed_widths_component.underflow_checking = "ON",

dcfifo_mixed_widths_component.use_eab = "ON",

dcfifo_mixed_widths_component.write_aclr_synch = "ON",

dcfifo_mixed_widths_component.wrsync_delaypipe = 4;

and a screenshot from Modelsim showing all signals from that dcfifo:

You can see there the output changes immediately with the same clock the read request is captured, I marked it with the cursor.

Best regards,

Erich