BUG in simulation library for dcfifo_mixed_widths with Modelsim

Hi Erich, from your forum post, not only forum got worst, also support people seems don't read messages before reply.

Are you Altera centric or use other competitor?

I collected some critics to new Altera behavior, I am just searching for information about bug on simulation release, hardware and correlated.

Most of time simulator crash or report error on VHDL syntax, valid syntax. I simulate on thirdy party or competitor to check just IP core.

When I come back to Quartus design sometimes work and no idea of how to close timing and synthesis to get things work.

I feel this forum is not the best, are you on a neutral one like http://www.fpgadeveloper.com/? Can we join there to get a free of fear opinion about not least share opinion about what to do in the future?

I never used Altera from MM Pal age, Philips PLA (nicr fuse) and Xilinx XACT to mention few.

I migrated to Altera near 2005, designed on near all firm. Luckily speaking I never made large number on this firm.

Previous week I told my custom I fear I am not able to complete design and upset with me due I choosed Altera, made prototypes and fail at production test stage. :(

Best regards

Roberto