Occasional Contributor
Occasional ContributorI did some further tests and I can bring some light into that issue. I analyzed it further and used the "Events mode" display in Modelsim.
I have now two examples where the same input is send to the FIFO. One time it behaves properly one time it fails.
The following situation is fine:
No signal or just the request signals are delayed with 23ps -> simulation works as you would expect.
In "Event Display mode" one can see that the clock is the first event and the read request signal comes later in the events.
The following situation it fails:
All the signals (including clock) are delayed by the same amount of time (23ps). So all the signals arrive the FIFO at the same time (as in the working situation described above)
In "Event Display mode" one can see that for any reason the read request signal is computed first. -> So with the next clock cycle (which actually had the rising edge at the same time as the request signal) the output is changed -> reason for the to early output.
So the behavior of that FIFO simulation model is weird. In my opinion if I look at it as a black box it should behave the same way if I input the same signals at any time!
Of course it is not the usual case to delay the clock signal and it is an edge case.
Best regards,
Erich
