Asynchronous Data Pulse Acquisition

Hi altera gurus,

First time poster here.

I've been teaching myself about writing VHDL, timing analysis, and test benches over the past few months while making a customized DSP application on an FPGA board for an experiment that I'm working with. But, I am running into an issue:

I have a Cyclone V with a 50MHz clock. I am receiving digitized pulses from a sensor that are 5 ns long and randomly (though generally sparsely) spaced. These pulses, naturally, are asynchronous, and they are also shorter (200MHz) than my clock domain (50MHz). So, I use the pulses in the sensitivity list of a process statement in an implementation of a flancter (link here) (https://www.doulos.com/knowhow/fpga/fastcounter/). I use these flancters to bring the data pulses into the clock domain, up / down counter them, do some other stuff, and put results in a FIFO.

Now, I've got 16 channels of this (later it will be 32 or even more). When I compile, timequest rightfully gives me a slew of warnings that these lines were "determined to be a clock but was found without an associated clock assignment." So, I modify the .sdc file with this line:

# Create a clock constraints for the asynchronous data inputs of the 16 channels.
create_clock -name "data_clks" -period 20.00ns {A
} -waveform {0.000 10.000}
set_clock_groups -asynchronous 
-group {data_clks}

Is this the right way to tell timequest and the fitting tools that this is an input that doesn't really matter in terms of clocks, since it's just an asynchronous pulse? Or should I handle the clock constraints differently?

As an aside, I made the above code before I knew that PLLs existed. So, if the above approach is a complete disaster I may just make a 400 MHz PLL from my system clock and use that with a couple shift registers to bring the 5 ns pulses into my clock domain. Thoughts on that approach?