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Honored Contributor
Honored ContributorAsynchronous Data Pulse Acquisition
Hi altera gurus, First time poster here. I've been teaching myself about writing VHDL, timing analysis, and test benches over the past few months while making a customized DSP application ...
Altera_ForumHonored Contributor
Honored ContributorNo - the SDC doesn't affect the number of registers you'll end up with. Only your code will do that. By using option 1 your code will only describe two registers, operating @ '100MHz', per sensor signal - what you'll end up with.
In order to over-sample the signals, as in option 2, you will simply end up with - or should I say likely to end up with, based on the implementation I have in my head - a greater number of registers operating at a much higher frequency, 400MHz. Each will need shifting in through 3 registers and you will then need further logic to detect the pulse and another register to latch it. So, I make that 4 registers for option 2. Given the device you're using and the number of registers we're talking about here, the 'clear advantage' as I put it isn't actually that great. However, in general, clocking logic more slowly makes everything a little easier. Yes, I agree with 10ns. Cheers, Alex
