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Altera_Forum
Honored Contributor
Honored ContributorAsynchronous Data Pulse Acquisition
Hi altera gurus, First time poster here. I've been teaching myself about writing VHDL, timing analysis, and test benches over the past few months while making a customized DSP application ...
Altera_ForumHonored Contributor
Honored ContributorTo understand if the timing constraint is correct, we should see the logic it's applied to.
I think that the problem of reading 5 ns pulses into a 50 MHz clock domain would be usually solved by a toggle synchronizer.
