Asynchronous Data Pulse Acquisition

Depending on your chosen device, speed grade and how fast it can comfortably be clocked, I'd consider option 2 and use a PLL to generate the higher clock. The downside, you're obviously going to be clocking more logic at a much higher frequency, even if you do the bare minimum before moving everything onto a clock domain operating at a lower frequency.

However, I see nothing wrong with option 1 - the clear advantages of operating only a handful of registers at the higher clock frequency. I think the only correction to the constraint you posted is to specify the period at 5 ns (not 20ns) - as you mentioned, the effective frequency of these 'clocks' is 200MHz.

Cheers,

Alex

PS. Just spotted Cyclone V - which should have no real issues solving this with a PLL.