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Altera_Forum
Honored Contributor
Honored ContributorAsynchronous Data Pulse Acquisition
Hi altera gurus, First time poster here. I've been teaching myself about writing VHDL, timing analysis, and test benches over the past few months while making a customized DSP application ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- However, I see nothing wrong with option 1 - the clear advantages of operating only a handful of registers at the higher clock frequency. --- Quote End --- Can you elaborate on this statement, please? I don't quite understand what you mean here. I'll try to write out my understanding of it, which might help you to see my issue: Is the sdc statement causing the fitting tools to make the required number of registers at the higher clock frequency and no more? I have been testing it a bunch on hardware since my original post, and it works (hooray!) even without the "period 5ns" change in the constraint. But I will put it in and test it just to be safe. Should it be 10ns for that constraint, since the pulse length is 5ns? I suggest this since it'd be 5ns "on" for that pulse and thus I add 5ns "off" for the "clock" period.
