New ContributorHi
I am using platform designer with the Arria10. I have two DDR3 memory interfaces which use clock sharing so they should share the same clock domain. Platform designer inserts clock crossing logic when accessing the memory interface I do not source the system clock from. Is there anyway to prevent this?
Regards,
Graeme
Super ContributorCan you show your PD system design? You should be connecting directly between the EMIF IP components.
New ContributorI am using core clock sharing and this is working. My question was related to platform designer, despite using core clock sharing to enable access to the two DDR interfaces synchronously - platform designer determines that the clocks are different and inserts unnecessary clock crossing logic in the interconnect. I would like to know if there is a recommended way to prevent this.
Super ContributorAre you talking about the reference clock or core clocks? For reference clock sharing, the interfaces must be physically adjacent in the same I/O column and the refclk should be input to both interfaces. For core clock sharing, you enable the sharing parameter to master in one interface and slave in the other and connect them together. These and other requirements documented here: https://docs.altera.com/r/5ybDUDNrbPzSEVSGXW2L4g/nuuBYVUSqwyh6I~S6g0WKg
