Forum Discussion
graememe
New Contributor
New ContributorArria10 Platform Designer EMIF
Hi I am using platform designer with the Arria10. I have two DDR3 memory interfaces which use clock sharing so they should share the same clock domain. Platform designer inserts clock crossing logic...
graememeNew Contributor
New ContributorI am using core clock sharing and this is working. My question was related to platform designer, despite using core clock sharing to enable access to the two DDR interfaces synchronously - platform designer determines that the clocks are different and inserts unnecessary clock crossing logic in the interconnect. I would like to know if there is a recommended way to prevent this.
