Forum Discussion
graememe
New Contributor
New ContributorArria10 Platform Designer EMIF
Hi I am using platform designer with the Arria10. I have two DDR3 memory interfaces which use clock sharing so they should share the same clock domain. Platform designer inserts clock crossing logic...
sstrell
Super Contributor
Super ContributorAre you talking about the reference clock or core clocks? For reference clock sharing, the interfaces must be physically adjacent in the same I/O column and the refclk should be input to both interfaces. For core clock sharing, you enable the sharing parameter to master in one interface and slave in the other and connect them together. These and other requirements documented here: https://docs.altera.com/r/5ybDUDNrbPzSEVSGXW2L4g/nuuBYVUSqwyh6I~S6g0WKg
