Hi,
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I am currently using a Cyclone 10 LP device with an EPCS16 program memory in Quartus Prime 17.1 and Platform Designer.
Is it possible to use the dedicated AS Pins as regular I/O together with the Altera Serial Flash Controller IP in this device?
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Yes,
1.In all Intel device families except Cyclone III, Cyclone IV, and Intel Cyclone 10 LP the EPCS serial flash controller core does not create any I/O ports on the top-level Platform Designer system module.
If the EPCS device and the FPGA are wired together on a board for configuration using the EPCS device (in other words, active serial configuration mode), no further connection is necessary between the EPCS serial flash controller core and the EPCS device.
2.When you compile the Platform Designer system in the Intel Quartus Prime software, the EPCS serial flash controller core signals are routed automatically to the device pins for the EPCS device.
3.You, however, have the option not to use the dedicated pins on the FPGA (active serial configuration mode) by turning off the respective parameters in the MegaWizard interface. When this option is turned off or when the target device is a Cyclone III, Cyclone IV device, or Intel Cyclone 10 LP you have the flexibility to connect the output pins, which are exported to the top-level design, to any EPCS devices by setting Dual-purpose pins.
For more information refer to section 14.2
https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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