altera_internal_jtag clock and timing issues

Question

Hi

I'm using Quartus 8.1 with SOPC builder including a NIOS and JTAG UART instantiation.

a long time ago I got failing paths in the Timequest analyzer, regarding clocks crossing between my system clock and altera_internal_jtag.

back then I simply defined the clock crossing as a false path, the red messages were gone and I was happy.:)

lately I got some very strange behavior from the design, function that works fine, stops or behave strangely when I use functions not related to them... in short a very unstable design.

today I compiled a design with one of this symptoms, recompiled it with a different seed, and the symptom was gone.

so obviously I suspect fitting and timing issues.

is there a better way to handle the jtag clock (other then set a false path)?

should it be defined in the SOPC builder as a clock?

should I use some kind of a bridge between the JTAG UART and the rest of the system?

who framed Roger Rabbit?

thanks in advance

Ron

altera_forum · Answer

The JTAG clock actually now has it's own built in false path. The JTAG clock has no timing relation to anything in the design, so if it worked with a different seed, then the problem doesn't have anything to do with this. (If it always failed, then there could potentially be a problem, but it would be with the logic, not the RTL, since there is no way to transfer data from the JTAG clock to other domains in a synchronous manner).

It does sound like you have a timing problem, but I'm guessing it's elsewhere, and will probably take some low-level debug. Good luck.

altera_forum · Answer

Hi Rysc

just to remind you, I'm still using 8.1, since when is the built in false path?

when I remove all the assignments in my sdc file, and leave only the clock definitions (which is very short, a clock from the outside world, that goes into a PLL that generates a single clock to drive all the rest of the logic) and the auto generated assignments created by the SOPC builder, I get report about failing paths, that cross to the jtag clock domain, and vice verse, no other paths.

so it is the immediate suspect...

altera_forum · Answer

Right, you have to do it yourself. In some version(I'm not sure which), there was a constraint embedded into the JTAG tap controller. So when TimeQuest excutes read_sdc, it gives a message:

Info: Evaluating HDL-embedded SDC commands

Info: Entity sld_hub

Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]

Info: set_clock_groups -asynchronous -group {altera_reserved_tck}

(I pulled that from a Stratix IV design I have). The set_clock_groups command is what cuts it from all other clocks in the design. Now, in 8.1 you pretty much had to do this yourself, but that just makes the timing errors go away, but won't fix the problem.

altera_forum · Answer

This issue is solved in Altera Knowledge base. The solution includes design constraints. Please do a search there before asking in the forum.

altera_forum · Answer

I am in need of higher clock more than 600MHz.... In Altera Fpga kit it has an internal clock upto 50Mhz. If i use any external clock source, which is going to be compatible? function generator or crystal oscillator. Is Crystal oscillator alone is enough to form the external clock.

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altera_internal_jtag clock and timing issues

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