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The JTAG clock actually now has it's own built in false path. The JTAG clock has no timing relation to anything in the design, so if it worked with a different seed, then the problem doesn't have anything to do with this. (If it always failed, then there could potentially be a problem, but it would be with the logic, not the RTL, since there is no way to transfer data from the JTAG clock to other domains in a synchronous manner).
It does sound like you have a timing problem, but I'm guessing it's elsewhere, and will probably take some low-level debug. Good luck.
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Hello! I'm a newcomer ,could you tell me how to set a current file(there are some vhdl files but how can I compile the file I want )?Thank you!!!
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