altera_internal_jtag clock and timing issues

Hi Rysc

just to remind you, I'm still using 8.1, since when is the built in false path?

when I remove all the assignments in my sdc file, and leave only the clock definitions (which is very short, a clock from the outside world, that goes into a PLL that generates a single clock to drive all the rest of the logic) and the auto generated assignments created by the SOPC builder, I get report about failing paths, that cross to the jtag clock domain, and vice verse, no other paths.

so it is the immediate suspect...