altera_internal_jtag clock and timing issues

Right, you have to do it yourself. In some version(I'm not sure which), there was a constraint embedded into the JTAG tap controller. So when TimeQuest excutes read_sdc, it gives a message:

Info: Evaluating HDL-embedded SDC commands

Info: Entity sld_hub

Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]

Info: set_clock_groups -asynchronous -group {altera_reserved_tck}

(I pulled that from a Stratix IV design I have). The set_clock_groups command is what cuts it from all other clocks in the design. Now, in 8.1 you pretty much had to do this yourself, but that just makes the timing errors go away, but won't fix the problem.