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Altera_Forum
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14 years ago

altera_internal_jtag clock and timing issues

Hi I'm using Quartus 8.1 with SOPC builder including a NIOS and JTAG UART instantiation. a long time ago I got failing paths in the Timequest analyzer, regarding clocks crossing between my...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

can any please help me? or direct me to the topic in the Altera knowledge base that Socrates refered to?

all I found is that the altera_internal_clock should be defined as 10MHz, but when I do that I get errors.

If I declare the clock crossing paths as false paths I'm back in square 1, with an unstable design.