altera_internal_jtag clock and timing issues

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Why do You need such fast clock? Dream on about having such on FPGA itself. You can only get such fast clock on transceiver block. Check Your FPGA datasheet for Fmax.

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I checked my data sheet, It says that It has three pins allocated for clock

1. 50 Mhz

2. 27Mhz

3. External clock

So where could i get my fast clock from Fpga itself.I would like know what is transceiver block. Thanks for your help.