Accessing SRAM from NIOS and Verilog Module

Question

Hi,

I have implemented the Web Server example on the DE2-115 and modified it a bit to send data over ethernet to the DE2-115 board and store it in the SRAM. This data is around 1Mbit . Next I want to send this data to the GPIO headers of the DE2-115 on a trigger signal. I want to send the data on the rising edge of the clock signal I recieve on SMA CLKIN. All I need for this is a simple verilog code that transfers data from SRAM to the GPIO pins. The SRAM is accessed by the NIOS processor but I want to use hardware to transfer data from the SRAM to the pins since I want a faster transfer rate than NIOS can achieve. Do I need to use SGDMA or is there a simpler solution for this? Any help would be appreciated. Thanks!

altera_forum · Answer

Yeah you should use SGDMA to transfer your data to SDRAM. Look up Modular SGDMA. There are a lot of threads and examples on this forum on how to use this SGDMA. You still need the nios to write descriptors to the SGDMA, but the actually data transfer is no handled by the NIOS so it is much faster.

altera_forum · Answer

Hi Kraser,  Thanks for the reply. As I understand it, I am already using SGDMA to transfer data to the SRAM. So you mean I need to use it again to transfer data from SRAM to the GPIO pins (and HSMC pins) on the DE2-115? And to finally add this code (where the trigger starts data transfer) , do I need to add a Qsys component to connect to the SGDMA? It would be great if you could refer me to some instructive example you know of. Thanks!

altera_forum · Answer

SGDMA IP might consume quite lots of resources and overkill for your simple requirement. If you're willing to spend some time studying avalon specification, it will be easy to build a custom GPIO module with avalon-mm master interface. Here's avalon specification  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

altera_forum · Answer

Hi Mini@nB,  Thanks for the suggestion. I went through the document regarding Avalon interfaces. So as I understand, I should create a GPIO module that does a master read operation of the SRAM and the output is produced on the GPIO pins at every clock cycle. I am assuming I need to modify the Avalon Memory-Mapped Master Template provided by Altera. And once I have a module I can add it to my Qsys system. I have two very basic questions. First, since I want to transfer data really fast from the SRAM to the GPIO(which are in turn connected to DDS boards) I would like to use an external clock. This will be connected to SMA CLKIN. So I am guessing I will need to include SMA CLKIN in my Qsys system as well. Am I on the right line of thought? Also, do I need to make any changes to the SRAM to make it accessible to both the NIOS processor (which stores data coming over ethernet to the SRAM)  and the GPIO pins. I am sorry if these questions are really silly or not structured well. I can elaborate more on my application if you want. Thanks!

altera_forum · Answer

The external clock and GPIO pins need to be exported out of Qsys system by declaring them as conduit interface in the spec. If SRAM is Avalon-mm slave, you just plug and play the master (make the connection) and the Avalon fabric will do the rest for you. One more thing you have to include an additional Avalon-mm slave control interface in your module that instruct how/when to transfer data from the memory.

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Accessing SRAM from NIOS and Verilog Module

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