Accessing SRAM from NIOS and Verilog Module

Hi Mini@nB,

Thanks for the suggestion. I went through the document regarding Avalon interfaces. So as I understand, I should create a GPIO module that does a master read operation of the SRAM and the output is produced on the GPIO pins at every clock cycle. I am assuming I need to modify the Avalon Memory-Mapped Master Template provided by Altera. And once I have a module I can add it to my Qsys system. I have two very basic questions. First, since I want to transfer data really fast from the SRAM to the GPIO(which are in turn connected to DDS boards) I would like to use an external clock. This will be connected to SMA CLKIN. So I am guessing I will need to include SMA CLKIN in my Qsys system as well. Am I on the right line of thought? Also, do I need to make any changes to the SRAM to make it accessible to both the NIOS processor (which stores data coming over ethernet to the SRAM) and the GPIO pins. I am sorry if these questions are really silly or not structured well. I can elaborate more on my application if you want. Thanks!